A method for the synthesis of stray-insensitive bandpass switched-capacitor filters (SCF's) using fully balanced switched-capacitor immittance converters (SCIC's) is presented. In the proposed method only one operational amplifier is needed per node (excluding the grounded node) in the passive ladder prototype.

This paper presents Bi-CMOS current-mode multiple valued logic circuit with 1.5 V supply voltage. This circuit is composed of current mirror, threshold detector and current source. This circuit has advantages such as high accuracy, high speed, high density and low supply voltage. So, it is possible to realize high-radix multiple valued logic circuit. As an other application of the proposed circuit, a processing unit of fuzzy inference is given. This circuit operates with high speed and high accuracy. The circuit simulation of the proposed circuit has been performed using SPICE2 program.

In this letter, a simple design of a discrete-time chaos circuit realizing a tent map is proposed. The proposed circuit can be constructed with 13 MOSFET's and 2 capacitors. Concerning the proposed circuit synthesized using switched-current (SI) techniques, the validity of the circuit design is analyzed by SPICE simulations. Furthermore, the proposed circuit is built with commercially-available IC's. The proposed circuit is integrable by a standard CMOS technology.

A low-sensitivity bandpass switched-capacitor filter (SCF) using two-path and voltage inversion techniques is proposed. The worstcase sensitivity of this SCF becomes zero at the center frequency. The proposed SCF is fully parasitic insensitive and requires a four-phase clock.

A capacitor-error-free SC voltage inverter with zero sensitivity to element-value variations is proposed. By virtue of the capacitor-error-free property, this SC voltage inverter is free from the capacitor mismatch. The performance of this SC voltage inverter has been confirmed from both the simulation and experiment.

For a realization of a DC-DC converter using no magnetic devices, a new switched capacitor (SC) transformer is introduced, which gives voltage ratios by Fibonacci series corresponding to the stages. This transformer is connected in cascade by each basic block which is assembled by a capacitor and three MOSFET switches. This operates on a simple two-phase clock and has a large step-up or step-down voltage ratio in spite of its simple configuration. The characteristics of this transformer with n stages of basic block are derived and calculated by means of a 4 4 cascade matrix. The optimal arrangement of each stage's capacitances is shown to reduce the SC resistance by about 20%. The simulation results are compared with the characteristics of a prototype transformer with four stages (8 times step-up ratio). Its power efficiency achieves 88% in case of 97 V output voltage, 0.2 A output current, and 100 kHz switching frequency. Lastly, the proposed SC transformer is compared and discussed with other typical SC transformers.

Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

New cyclic switched-capacitor (SC) D/A and A/D converters are proposed. In the former, a capacitor-mismatch-compensation technique using additional small capacitors is introduced. With this, a capacitor ratio accuracy as high as twelve bits is possible. And, in the latter, the A/D conversion with ten-bit accuracy is realizable by the simple ratio-independent circuit consuming only a few number of clock cycles for each bit conversion.

In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.

New AC-DC converters using switched-capacitor (SC) transformers are presented. The features of these circuits are as follows. (1) It does not contain any magnetic material. (2) The inrush current of the proposed converter is very small as compared with that of a condenser-input-type rectifier circuit. (3) It is realizable in a hybrid IC form. (4) It excels in size and weight when compared with reactor-type switching regulators of the same output power. As an example, an AC-DC converter using step-up SC transformers was built and tested to confirm the characteristics. The measured characteristics showed good agreement with the calculated ones.

This paper describes a single-bit parallel processor specified to Boltzmann Machine. The processor has SIMD (Shingle Instruction Multiple Data stream) type parallel architecture and every processing element (PE) has a single-bit ALU and a local memory storing connected weights between neurons. Features of the processor are large scale parallel processing a number of the simple single-bit PEs and effective expansion realized by multiple chips connected simple bus lines. Moreover, it is enhanced that the processing speed can be independent of the number of the neurons. We designed the PE using 1.2 µm CMOS process standard cells and confirmed the high performance using CAD simulations.

A maximum and a minimum circuits with multiple inputs are proposed. The operating speeds of these circuits are independent of the number of the inputs. Since the proposed circuits consist of only NMOS transistors, they can be implemented in semi-custom IC forms. A potential application of these circuits is a real-time fuzzy controller.

A fuzzy microprocessor is developed using 1.2 µm CMOS process. The inference scheme for the if-then fuzzy rules consists of three main steps i. e. if-part process, then-part process and defuzzification. In order to realize very high-speed inference and moderate programmability, we introduce three-type different structures i.e. SIMD, logic-in-memory and Wallace tree structures which are suitable for the three main steps. The inference speed including defuzzification is 7.5 MFLIPS which is 12.9 times higher than the previous VLSI implementation, and it can carry out many rules (960 rules) and many input and output variables (16 variables).

New OTA-based analog circuits for realizing fuzzy membership functions and maximum (MAX) and minimum (MIN) operations are proposed. The synthesis of these circuits based on a bounded-difference operation and their SPICE simulations are described.

A low-sensitivity lowpass switched-capacitor filter (SCF) whose worstcase sensitivity becomes zero at zero frequency is presented. The proposed SCF is realized with the fully balanced SC circuits using the op-amps which can provide the outputs of both signs.

The realization and the design of three types of low-sensitivity leapfrog switched-capacitor filters (SCF's) are proposed. These SCF's realized with new differential-mode building blocks exhibit an excellent reduction in worstcase sensitivity to component variations. The design for each proposed SCF was confirmed by the experiment. Since the proposed SCF's are all parasitics-compensated, they are realizable in MOS IC forms.